Bit

Mux(a=o2, b=in, sel=load, out=o1);
DFF(in=o1,out=o2);
And(a=o2,b=o2,out=out);

Register

Bit(in=in[0],load=load, out=out[0]);
// ...
Bit(in=in[15],load=load, out=out[15]);

PC

Inc16(in=new, out=newInc);
Mux16(a=new, b=newInc, sel=inc, out=o1);
Mux16(a=o1, b=in, sel=load, out=o2);
Mux16(a=o2, b=false, sel=reset, out=o3);
Register(in=o3, load=true, out=new, out=out);

RAM8

DMux8Way(in=load,sel=address, a=a0, b=a1, c=a2, d=a3, e=a4, f=a5, g=a6, h=a7);
Register(in=in,load=a0,out=o1);
Register(in=in,load=a1,out=o2);
Register(in=in,load=a2,out=o3);
Register(in=in,load=a3,out=o4);
Register(in=in,load=a4,out=o5);
Register(in=in,load=a5,out=o6);
Register(in=in,load=a6,out=o7);
Register(in=in,load=a7,out=o8);
Mux8Way16(a=o1,b=o2,c=o3,d=o4,e=o5,f=o6,g=o7,h=o8, sel=address, out=out);

RAM64

DMux8Way(in=load, sel=address[3..5], a=ram0,b=ram1,c=ram2,d=ram3,e=ram4,f=ram5,g=ram6,h=ram7);
RAM8(in=in,load=ram0,address=address[0..2],out=o0);
RAM8(in=in,load=ram1,address=address[0..2],out=o1);
RAM8(in=in,load=ram2,address=address[0..2],out=o2);
RAM8(in=in,load=ram3,address=address[0..2],out=o3);
RAM8(in=in,load=ram4,address=address[0..2],out=o4);
RAM8(in=in,load=ram5,address=address[0..2],out=o5);
RAM8(in=in,load=ram6,address=address[0..2],out=o6);
RAM8(in=in,load=ram7,address=address[0..2],out=o7);
Mux8Way16(a=o0,b=o1,c=o2,d=o3,e=o4,f=o5,g=o6,h=o7, sel=address[3..5], out=out);

RAM512

DMux8Way(in=load, sel=address[6..8], a=ram0,b=ram1,c=ram2,d=ram3,e=ram4,f=ram5,g=ram6,h=ram7);
RAM64(in=in,load=ram0,address=address[0..5],out=o0);
RAM64(in=in,load=ram1,address=address[0..5],out=o1);
RAM64(in=in,load=ram2,address=address[0..5],out=o2);
RAM64(in=in,load=ram3,address=address[0..5],out=o3);
RAM64(in=in,load=ram4,address=address[0..5],out=o4);
RAM64(in=in,load=ram5,address=address[0..5],out=o5);
RAM64(in=in,load=ram6,address=address[0..5],out=o6);
RAM64(in=in,load=ram7,address=address[0..5],out=o7);
Mux8Way16(a=o0,b=o1,c=o2,d=o3,e=o4,f=o5,g=o6,h=o7, sel=address[6..8], out=out);

RAM4K

DMux8Way(in=load, sel=address[9..11], a=ram0,b=ram1,c=ram2,d=ram3,e=ram4,f=ram5,g=ram6,h=ram7);
RAM512(in=in,load=ram0,address=address[0..8],out=o0);
RAM512(in=in,load=ram1,address=address[0..8],out=o1);
RAM512(in=in,load=ram2,address=address[0..8],out=o2);
RAM512(in=in,load=ram3,address=address[0..8],out=o3);
RAM512(in=in,load=ram4,address=address[0..8],out=o4);
RAM512(in=in,load=ram5,address=address[0..8],out=o5);
RAM512(in=in,load=ram6,address=address[0..8],out=o6);
RAM512(in=in,load=ram7,address=address[0..8],out=o7);
Mux8Way16(a=o0,b=o1,c=o2,d=o3,e=o4,f=o5,g=o6,h=o7, sel=address[9..11], out=out);

RAM16K

DMux4Way(in=load, sel=address[12..13], a=ram0,b=ram1,c=ram2,d=ram3);
RAM4K(in=in,load=ram0,address=address[0..11],out=o0);
RAM4K(in=in,load=ram1,address=address[0..11],out=o1);
RAM4K(in=in,load=ram2,address=address[0..11],out=o2);
RAM4K(in=in,load=ram3,address=address[0..11],out=o3);
Mux4Way16(a=o0,b=o1,c=o2,d=o3, sel=address[12..13], out=out);